
Artificial intelligence chip makers include accelerator designers such as NVIDIA, AMD, and Intel; cloud companies building custom processors, including Google, AWS, and Microsoft; and specialists such as Cerebras, Groq, SambaNova, and Tenstorrent. Apple and Qualcomm develop chips for on-device AI. Foundries such as TSMC manufacture designs for customers, which is a different role from selling a complete AI computing platform.
These companies do not all compete for the same purchase. A team renting GPU servers, a developer using an inference API, and a manufacturer choosing a processor for a device need different suppliers. Understanding that distinction makes a company list useful.
The examples below were checked against official product pages and announcements on October 14, 2026. They describe product families and access routes, not a market-share ranking or a claim that every listed system is available in every region.
The phrase “chip maker” often combines several jobs. A company can design a processor without owning the factory that fabricates it. Another may manufacture the silicon, supply memory, package several components together, or build the server that customers use.
| Role | What it provides | Example |
|---|---|---|
| Accelerator designer | Processor architecture, chips, and supporting software | NVIDIA GPUs; AMD Instinct; Intel Gaudi |
| Cloud custom-silicon developer | Processors integrated into its cloud infrastructure | Google TPU; AWS Trainium; Microsoft Maia |
| Specialist processor company | An alternative architecture and its deployment software | Cerebras; Groq; SambaNova; Tenstorrent |
| Device processor designer | AI acceleration within a phone, laptop, or embedded platform | Apple silicon; Qualcomm Snapdragon |
| Foundry and manufacturing supplier | Fabrication or other production services for chip designs | TSMC's customer manufacturing model |
GPU, TPU, NPU, and ASIC are also different kinds of labels. GPU describes a processor architecture, NPU describes a neural-processing role, and ASIC means a chip designed for a particular application. A TPU is an ASIC, but that does not mean it runs only one fixed model. Our guide to AI accelerators explains the hardware categories in more detail.
Many machine learning calculations operate on tensors, which are arrays of values. AI processors often include parallel execution units and specialized matrix arithmetic to handle these operations. CPUs still perform useful work, including application control and data preparation; modern CPUs can also execute parallel calculations.
Numeric precision affects both speed and memory demand. Lower-precision formats can reduce the amount of data processed and stored, but the model must still meet its quality target. A peak figure calculated with sparse, low-precision operations is not directly comparable with a dense, higher-precision result.
Training and inference also stress hardware differently. Training must accommodate the model's learning process and associated state. Inference serves a trained model, with memory and response behavior affected by batch size, context length, and concurrent requests. Memory capacity, bandwidth, and communication between chips can become limiting factors before peak arithmetic throughput is reached.
That is why chip design and software development are closely connected. An operation that the hardware supports in principle still needs a working compiler, kernel, and runtime path in the deployed application.
NVIDIA designs GPUs and the software and interconnects used around them. Its Blackwell platform illustrates the system-level approach: the processor, memory, connections between accelerators, and deployment configuration all affect the result. Customers encounter NVIDIA hardware through server vendors, cloud providers, and complete systems.
For a development team, the practical question is whether its frameworks, libraries, and model implementations support the chosen GPU. A newer product announcement does not make an existing supported system unusable. Compare the specific hardware and software configuration you can obtain.
AMD's Instinct accelerators serve data-center AI and high-performance computing. Its catalog includes the MI400 family alongside earlier generations. AMD also develops the ROCm software platform used to program and deploy supported accelerators.
Evaluate the exact model, operating system, framework version, and kernels your application needs. A framework being available on two vendors' platforms does not guarantee identical extension support, installation steps, or performance. Include any porting and validation work in the comparison.
Intel's Gaudi accelerator family includes Gaudi 3 for AI workloads, with an associated software stack and system configurations. Treat those systems as specific deployment options rather than assuming every Intel-based machine contains a Gaudi accelerator.
Keep the CPU and accelerator roles separate when reading specifications. The host processor, AI accelerator, network, and memory can each limit a job. A broad claim that one company's chip is several times faster is not enough without the model, precision, system size, and test conditions.
Google designs Tensor Processing Units and makes supported configurations accessible through Google Cloud. Its current TPU catalog lists Ironwood as generally available and distinguishes it from the forthcoming TPU 8t and TPU 8i. That status distinction matters when planning a deployment.
A TPU choice includes the available cloud configuration, supported software, capacity, and data location. Compare the full service with a GPU alternative rather than comparing a chip's theoretical arithmetic throughput with a rented server's application result.
AWS develops Trainium and Inferentia processors. Trainium is not limited to training: EC2 Trn3 UltraServers, powered by Trainium3, support training and inference through the AWS Neuron software stack. The product is an available service family, not merely a planned late-2025 release.
Check model support, compiler behavior, instance capacity, and the AWS services your application uses. Moving from a GPU implementation can require changes even when the high-level framework is familiar. A quoted performance improvement needs the benchmark configuration behind it.
Microsoft develops Maia accelerators for its AI infrastructure. In its October 2026 update, Microsoft says Maia 200 is serving production workloads and Maia 300 is coming in 2027.
That announcement does not establish that a reader can order a Maia 300 server or rent an unrestricted instance today. Distinguish an accelerator used within a provider's services from a public infrastructure product with documented customer access. Evaluate the service you can actually use.
Cerebras develops wafer-scale processors, using a much larger piece of silicon than a conventional individual chip. Its current wafer-scale product page describes WSE-3 Turbo and CS-4 systems. This is a different system architecture from attaching several ordinary GPU cards to a server.
Compare supported workloads and access options at the system or service level. Cerebras compute-core counts and on-chip memory bandwidth are not interchangeable with GPU core counts and external-memory bandwidth.
Groq develops inference technology and provides access through GroqCloud. Its relationship with NVIDIA changed through a non-exclusive licensing agreement announced in December 2025. The announcement states that Groq would remain an independent company and GroqCloud would continue operating.
For an application team, test the models, context limits, request limits, and response behavior offered by the service. A high generation speed for one model does not establish the same result for another model or a different concurrency level.
SambaNova develops Reconfigurable Dataflow Units, or RDUs, and systems built around them. Its RDU product documentation describes the SN50 generation and its use of multiple memory tiers for inference.
Assess the supported models and the complete deployment, including any other accelerators involved. Avoid translating a processor's peak specification into a universal application speedup. Inference may include separate stages with different compute and memory requirements.
Tenstorrent develops AI processors and software, including its Blackhole family. Its Blackhole developer-product announcement describes PCIe cards, integrated RISC-V cores, and open-source software components.
Open-source software is useful for inspection and development, but it does not automatically make every model portable or every hardware design openly licensed. Check the license and compatibility of each component, together with the maturity of the workload you want to run.
Apple integrates AI-capable components into its own devices. The M5 announcement, for example, describes a Neural Engine and GPU Neural Accelerators within a system on a chip. That illustrates why “AI chip” does not always mean a separate accelerator card.
For local applications, check the supported device, memory capacity, operating system, and execution framework. Buying a device with AI acceleration is a different decision from renting a multi-accelerator data-center system.
Qualcomm's Hexagon NPU is part of its approach to on-device AI across supported platforms. CPU, GPU, and NPU resources may work together rather than placing every operation on one processor.
The useful measure is whether the application runs within the device's memory, power, and response-time constraints. On-device processing can reduce dependence on a remote service for supported tasks, but the chip name alone does not prove that an application keeps all data local.
TSMC's foundry business focuses on manufacturing customers' products. Its role differs from a company offering a branded accelerator and software platform. Buying a GPU from a designer or server supplier does not mean buying fabrication services directly from TSMC.
Custom-silicon partners also matter. Broadcom's custom-accelerator platform describes work spanning compute design implementation, memory integration, networking, and packaging. It is another reason to avoid treating every company in an AI semiconductor list as a direct substitute for NVIDIA or AMD.
Memory is a separate part of the supply chain. Suppliers such as Micron provide high-bandwidth memory used in accelerator systems. Fabrication, memory, packaging, server assembly, power, and cooling all contribute to a usable deployment. A processor announcement does not establish delivery capacity for the whole system.
Start with the work you need to complete. Training, fine-tuning, interactive inference, and batch inference have different requirements. A small model can also run adequately on a CPU, so an accelerator should solve a demonstrated need.
| Question | Evidence to request | Common comparison error |
|---|---|---|
| Will the model run correctly? | Supported operators, precision, framework versions, and quality checks | Assuming framework support covers every extension |
| Will it fit? | Memory needed for weights, cache, activations, and runtime overhead | Comparing only model-file size with advertised memory |
| Will users get acceptable responses? | Time to first token, generation rate, concurrency, and tail latency | Using peak tokens per second as the only measure |
| Can the workload scale? | Multi-device tests and network configuration | Multiplying one-device throughput by the device count |
| What will successful work cost? | End-to-end runtime, utilization, setup effort, and total charges | Choosing the lowest hourly rate without measuring completion time |
Do not compare vendor core counts as though every core performs the same work. TOPS and FLOPS also depend on numeric precision and whether a result assumes sparsity. Distinguish one accelerator from a node, rack, or complete cluster.
MLPerf Inference results provide a structured starting point for supported workloads. Read the benchmark version, scenario, quality requirement, and submitted system configuration. A reproducible benchmark is useful evidence, but your own model and traffic pattern still need testing.
Our comparison of AI accelerators and GPUs for inference develops those workload questions. Avoid treating market capitalization, funding totals, or an old market-size forecast as evidence that a chip will fit your application.
There are three common routes: buy a system, rent computing resources, or use a managed inference service. Ownership gives you control but adds procurement and operations. Rental provides access to a defined configuration while leaving you responsible for the software within your environment. A managed API handles more infrastructure but limits you to its supported features and models.
Use our AI compute rental guide when the question is how to test a workload without buying servers. Compute with Hivenet is a CPU and GPU compute service, not an AI chip manufacturer. Match its current configurations to your software and capacity requirements.
For any provider, verify availability, access permissions, data location, storage, transfer charges, and the process for stopping billable resources. Rental can avoid an initial hardware purchase; it does not guarantee the lowest total cost.
Record the exact hardware and software versions with the results. A change in quantization, kernel implementation, batching, or model version can change the comparison without any change to the chip itself.
Examples include NVIDIA, AMD, Intel, Google, AWS, Microsoft, Cerebras, Groq, SambaNova, Tenstorrent, Apple, and Qualcomm. They cover different architectures and markets. Foundries and memory suppliers contribute to production without necessarily offering a competing computing service.
A fabless company designs chips and uses manufacturing partners to fabricate them. A foundry provides that fabrication service. Evaluate the finished product and supplier commitments rather than assuming that the company whose name appears on a chip owns its factory.
No. Their value depends on the supported workload, software, memory, utilization, and complete system cost. A specialized processor may suit one deployment while a GPU offers the flexibility needed for another.
Separate the announcement date from production, customer availability, and availability in your required region. Treat performance claims as conditional on their test configuration, and do not build a delivery plan around hardware you cannot yet obtain.
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